AMD 2006 Annual Report Download - page 172

EXECUTION VERSION
“Background Know-How” means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the
performance of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3.
Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist Technology, Stand Alone Memory, SiGe Technology,
Chip Designs or Post-Silicon Devices.
“BEOL” (Back End of Line) shall mean those aspects of Background Know-How and Specific Results that are directed to methods and processes of
interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a dielectric,
up to and including polyimide passivation and final via formation but not including Bump Technology and Packaging Technology. For the avoidance of doubt,
“BEOL” shall not include local interconnects made of tungsten.
“Bulk CMOS” means 90nm, 65nm and 45nm CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.
“Bulk CMOS Information” means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or
(ii) selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4. For the avoidance of doubt, Bulk CMOS
Information shall not include any eDRAM Technology derived from or used in CMOS 12SeD.
“Bump Technology” means the technology associated with connecting an Integrated Circuit to a chip carrier including IBM’s collapsible chip carrier connection
(“C4”) interconnect technology as further defined in Exhibit A that is developed during the term if this Agreement for use with, but not limited to, the
semiconductor process technologies also developed under this Agreement. Bump Technology shall include the following process steps: bump limiting metallurgy
deposition, photolithography, solder deposition, etching, solder reflow and cleaning, and non-solder interconnect technology.
“***” shall mean *** and its subsidiaries located in ***.
“***-AMD Manufacturing Facility” shall mean any facility for the manufacture of Integrated Circuits located in *** or Dresden, Germany and either owned
entirely by *** and AMD or owned by ***, AMD and all of the remaining such ownership interest is solely owned or controlled, directly or indirectly, by a
government entity or one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development,
manufacture, marketing or sale of Semiconductor Products.
“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random
access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip
Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process
development, (ii) process kerf test structures, layout, and data of the test chip(s) (including
***Confidential Treatment Requested.
Third Amendment and Restatement of “S” Process Development Agreement between AMD and IBM
IBM - AMD Confidential Page 4 of 90
Source: ADVANCED MICRO DEVIC, 10-K, March 01, 2007