AMD 1994 Annual Report Download - page 254

EXHIBIT B (1.4, 1.7, 1.8)
QUALIFICATION REQUIREMENTS AND PLAN
I. QUALIFICATION REQUIREMENTS:
1. The process and product qualification requirements are described in the
following AMD controlled documents:
--Fab Process Technology Qualification Specification # 00.021.2 Revision D
--Product Reliability Qualification Specification # 00.021.4 Revision A
2. TSMC will be manufacturing sorted die for AMD. The Acceptance Criteria for
the die will be based on three criteria. The criteria will be Wafer Electrical
Test (WET), Wafer Sort Yield, and Die Visual Quality.
A. WET criteria will be based on the measurements of TSMC test structures
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prior to wafer sort. All test structures will reside on nine sites per wafer.
The test structure minimum, maximum, and target will be defined and agreed upon
by the parties and be incorporated by reference in this Exhibit.
[CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND
EXCHANGE COMMISSION] of the wafers will be tested at WET. If a test is outside
of the minimum - maximum range, that will constitute a failure at that site. If
there are greater than [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY
WITH THE SECURITIES AND EXCHANGE COMMISSION] failures out of [CONFIDENTIAL
INFORMATION OMITTED AND FILED SEPARATELY WITH THE SECURITIES AND EXCHANGE
COMMISSION] WET site tests on a wafer for the same test, the wafer will be
considered as failing the WET criteria. If the wafer is outside the WET range
due to engineering tests, it will be accepted; if it is outside the range due to
processing issues, then it will be a candidate for scrap. The final decision on
scrap will be made by the joint AMD-TSMC disposition review process.
B. The Wafer Sort Criteria will initially be set such that any wafers with a
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yield of less than [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH
THE SECURITIES AND EXCHANGE COMMISSION] and any lots with an average yield of
less than [CONFIDENTIAL INFORMATION OMITTED AND FILED SEPARATELY WITH THE
SECURITIES AND EXCHANGE COMMISSION] (for the lot size of those wafers entering
sort--accounting for fab yield and WET rejection) will be scrapped. (Changes in
die size can trigger a review of these initial scrap limits if requested by
TSMC). Recognizing that product reliability is heavily dependent on defect
levels, these scrap limits will be reviewed by AMD and TSMC on a semi-annual
basis and adjusted upward as yield improves. New limits should be set based on
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yield data from the latest six (6) months of production.
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Source: ADVANCED MICRO DEVIC, 10-K, March 07, 1995