Crucial 2014 Annual Report Download - page 9

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Product Warranty
Because the design and manufacturing process for semiconductor products is highly complex, it is possible that we may
produce products that do not comply with customer specifications, contain defects or are otherwise incompatible with end
uses. In accordance with industry practice, we generally provide a limited warranty that our products are in compliance with
our specifications existing at the time of delivery. Under our general terms and conditions of sale, liability for certain failures
of product during a stated warranty period is usually limited to repair or replacement of defective items or return of, or a credit
with respect to, amounts paid for such items. Under certain circumstances, we provide more extensive limited warranty
coverage than that provided under our general terms and conditions.
Competition
We face intense competition in the semiconductor memory market from a number of companies, including Samsung
Electronics Co., Ltd.; SanDisk Corporation; SK Hynix Inc. and Toshiba Corporation. Some of our competitors are large
corporations or conglomerates that may have greater resources to withstand downturns in the semiconductor markets in which
we compete, invest in technology and capitalize on growth opportunities. Our competitors seek to increase silicon capacity,
improve yields, reduce die size and minimize mask levels in their product designs resulting in significantly increased
worldwide supply and downward pressure on prices. Many of our high-volume memory products are manufactured to industry
standard specifications and as such have similar performance characteristics to those of our competitors. For these high-
volume memory products, the principal competitive factors are generally price and performance characteristics including:
operating speed, power consumption, reliability, compatibility, size and form factors. For our other memory products, the
aforementioned performance characteristics generally take precedence to pricing.
Research and Development
Our process technology R&D efforts are focused primarily on development of successively smaller line-width process
technologies, as well as new, fundamentally different memory structures, materials and packages, which are designed to
facilitate our transition to next generation memory products. Additional process technology R&D efforts focus on the
enablement of advanced computing and mobile memory architectures, the investigation of new opportunities that leverage our
core semiconductor expertise and the development of new manufacturing materials. Product design and development efforts
include our high density DDR3 and DDR4 DRAM and LPDRAM products as well as high density and mobile NAND Flash
memory (including 3D NAND and MLC and TLC technologies), NOR Flash memory, specialty memory, SSDs, HMCs and
other memory technologies and systems.
Our R&D expenses were $1.37 billion, $931 million and $918 million in 2014, 2013 and 2012, respectively. We share
certain R&D process technology and design costs for NAND Flash and emerging technologies with Intel. We shared R&D
process and design costs for DRAM with Nanya through December 2012, when our cost-sharing agreement was terminated.
As a result of reimbursements under our Intel and Nanya cost-sharing arrangements, our overall R&D expenses were reduced
by $137 million, $146 million and $225 million in 2014, 2013 and 2012, respectively.
To compete in the semiconductor memory industry, we must continue to develop technologically advanced products and
processes. We believe that expansion of our semiconductor product offerings is necessary to meet expected market demand for
specific memory solutions. Our process, design and package development efforts occur at multiple locations across the world,
with our largest R&D centers located in Boise, Idaho; Hiroshima, Japan; Hashimoto, Japan; and Milpitas, California. We have
several additional product design centers in other strategic locations around the world. In addition, we develop
photolithography mask technology at our MP Mask joint venture facility in Boise.
R&D expenses vary primarily with the number of development wafers processed, the cost of advanced equipment
dedicated to new product and process development and personnel costs. Because of the lead times necessary to manufacture
our products, we typically begin to process wafers before completion of performance and reliability testing. We deem
development of a product complete once the product has been thoroughly reviewed and tested for performance and reliability.
R&D expenses can vary significantly depending on the timing of product qualification.