AMD 2002 Annual Report Download - page 240

“AMD Deputy Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.2 below.
“ASIC Product” shall mean an SOI Integrated Circuit that is not a Foundry Product and wherein all of the following conditions are met: (i) at least one of (a) the
functional requirements, or (b) the design, for such SOI Integrated Circuit product is provided to a Party from a Third Party; (ii) such Party participated in an
aspect of the definition and design of such product; and (iii) such Party is contractually bound to manufacture such product solely for, and to sell such product
solely to, such Third Party or its distributor or other recipient solely for the benefit of such Third Party.
“Background Know-How” means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the
performance of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3.
Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist Technology, Memory, SiGe Technology, or Chip
Designs.
“BEOL” (Back End of Line) shall mean those aspects of Background Know-How and Specific Results that are directed to methods and processes of
interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a dielectric,
up to and not including Packaging Technology. For the avoidance of doubt, “BEOL” shall not include local interconnects made of tungsten.
“Bulk CMOS” shall mean CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.
“Bulk CMOS Information” shall mean those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii)
selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4.
“Chip Design(s)” shall mean any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation)
random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry;provided, however, that
“Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process
development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells) as well as such test chips themselves used for the
development work of the Process Development Projects unless specifically excluded, or (iii) other product designs as mutually agreed by the Parties to be used as
qualification vehicles in the Process Development Projects. For the avoidance of doubt, all of (i) through (iii) above shall be treated as Specific Results to the
extent utilized in a Process Development Project.
Source: ADVANCED MICRO DEVIC, 10-K, March 14, 2003