SanDisk 2004 Annual Report Download - page 35

Table of Contents
and ultra clean environment. Semiconductor manufacturing yields and product reliability are a function of both design technology and
manufacturing process technology and production delays may be caused by equipment malfunctions, fabrication facility accidents or
human errors. Yield problems may not be identified or improved until an actual product is made and can be tested. As a result, yield
problems may not be identified until the wafers are well into the production process. We have from time to time experienced adverse
yields which have adversely affected our business and results of operations. We have experienced adverse yields on more than one
occasion when we have transitioned to new generations of products. If actual yields are low, we will experience higher costs and
reduced product availability, which could harm our business, financial condition and results of operations. For example, in 2005, we
expect to begin transitioning from 90−nanometer technology to 70−nanometer technology at FlashVision. If yields from the
70−nanometer wafers do not improve as expected, our business, financial condition and results of operations will be harmed.
In transitioning to new processes and products, we face production and market acceptance risks that have caused, and may in the
future cause, significant product delays that could harm our business. Successive generations of our products have incorporated
semiconductors with greater memory capacity per chip. The transition to new generations of products is highly complex and requires
new controllers, new test procedures and modifications of numerous aspects of manufacturing, as well as extensive qualification of the
new products by both us and our OEM customers. Any material delay in a qualification schedule could delay deliveries and adversely
impact our operating results. We periodically have experienced significant delays in the development and volume production ramp−up
of our products. Similar delays could occur in the future and could harm our business, financial condition and results of operations.
We and Toshiba plan to continue to expand the wafer fabrication capacity of our FlashVision and Flash Partners business
ventures in Japan and as we do so, we will make substantial capital investments and incur substantial start−up and tool relocation
costs, which could adversely impact our operating results. We and Toshiba plan to make substantial investments in new capital assets
to expand the wafer fabrication capacity of our FlashVision and Flash Partners business ventures in Japan. Each time that we and
Toshiba add substantial new wafer fabrication capacity, we will experience significant initial design and development and start−up
costs as a result of the delay between the time of the investment and the time qualified products are manufactured and sold in volume
quantities. For several quarters, we will incur initial design and development costs and start−up costs and pay our share of ongoing
operating activities even if we do not achieve the planned output volume or utilize our full share of the expanded output, and these
costs will impact our gross margins, results of operations and financial condition
Neither we nor Toshiba have operated 300−millimeter flash memory wafer manufacturing lines and there is no assurance that
Flash Partners’ facility will perform as expected. We believe that our future success will continue to depend on the development and
introduction of new generations of flash memory wafers, such as the 300−millimeter wafers to be produced by Flash Partners. These
wafers are substantially larger in surface area and therefore more susceptible to new technological and manufacturing issues, such as
mechanical and thermal stresses, than the current, mature 200−millimeter wafers that we use in production at Yokkaichi Fabs 1 and 2.
Toshiba does not have prior experience in manufacturing 300−millimeter advanced NAND designs, nor in operating a new equipment
set that has to be optimized to process 300−millimeter NAND wafers with competitive yields. Moreover, we have no experience in
operating a wafer manufacturing line and we rely on Toshiba’s capability to operate and manage the Yokkaichi facilities. This reliance
will increase when the Fab 3 facility commences operations. During the early stages of operating the new 300−millimeter wafer
processing equipment, we expect the venture to generate a large number of test wafers and perform numerous process test splits that
will increase our research and development expenses through most of 2005, prior to benefiting from any actual production output from
Fab 3. We cannot assure you that Flash Partners’ facility will perform as expected or be ready for volume production on time. Nor can
we assure you that the cost to equip the facility will not be significantly more than planned. Samsung, the world’s largest NAND flash
memory manufacturer, already has experience manufacturing 300−millimeter wafers with 90−nanometer feature sizes. Also, Samsung
is licensed under our patents to use MLC technology, which further enhances its manufacturing capabilities.
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