AMD 2008 Annual Report Download - page 26

The Foundry Company will provide certain foundry services to us. In August, 2008, we, on behalf of The
Foundry Company, extended our JDA with IBM through December 31, 2015 and added 32-nanometer and
22-nanometer “bulk” Industry Standard technology projects to the existing “SOI” High-Performance
development and research projects as part of the strategy to develop the manufacturing technology for a broader
potential Foundry Company customer base. The JDA will be assigned to The Foundry Company upon
consummation of The Foundry Company manufacturing joint venture transaction.
Manufacturing, Assembly and Test Facilities
During 2008, we owned and operated five manufacturing facilities. Our microprocessor manufacturing was
conducted at the facilities described in the chart below.
Facility Location
Wafer Size
(diameter in
millimeters)
Principal
Production
Technology
(in nanometers)
Approximate
Clean Room
Square
Footage
Dresden, Germany
Fab38 ............................ 300 65 263,000
Fab36 ............................ 300 65,45 150,000
During 2008, we manufactured our microprocessor products at Fab 36 primarily on 65-nanometer process
technology. At the same time, we also began the transition to 45-nanometer process technology at Fab 36, which
we expect to be completed by mid-2009. The full conversion of Fab 38 to 300-millimeter was delayed; rather Fab
38 was used to provide incremental capacity to Fab 36.
We have sourcing and manufacturing technology agreements with Chartered Semiconductor Manufacturing
pursuant to which Chartered is an additional manufacturing source for our microprocessors. We also have
foundry arrangements with third parties for the production of our embedded processors, chipset products and
graphics products.
With respect to our graphics and chipset products, we have strategic relationships with three semiconductor
foundries, Taiwan Semiconductor Manufacturing Company (TSMC), United Microelectronics Corp. (UMC) and
Chartered. Currently, we are in volume production in TSMC’s and UMC’s 300-millimeter fabrication facilities.
As of December 27, 2008, our graphics and chipsets were manufactured on 55-, 65-, 80-, 90-, 110-, 130-, 150- or
180- nanometer process technologies at third party foundries. Smaller process geometries can lead to gains in
graphics processing performance, lower power consumption and lower per unit manufacturing costs. We are
currently in the process of qualifying 40-nanometer process technology for certain products and expect to release
these products in the second half of 2009.
We outsource board-level graphics product manufacturing to third-party manufacturers. These include
Foxconn and PC Partner with locations in China. Our facility in Markham, Ontario, Canada is primarily devoted
to prototyping for new graphics product introductions.
Upon consummation of the transactions contemplated by the Master Transaction Agreement, we would
purchase substantially all of our microprocessor products from The Foundry Company pursuant to the terms of
the Wafer Supply Agreement. We would be able to use another foundry company as a second source for certain
of our quarterly microprocessor product wafer requirements and may source additional amounts from such
foundry company to the extent The Foundry Company is unable to deliver products to us sufficient to meet our
material customer commitments. In addition, once The Foundry Company establishes a 32-nanometer qualified
process, we would purchase from The Foundry Company, where competitive, specified percentages of our GPU
requirements, which percentage is expected to increase over a five-year period. We agreed not to sell, transfer or
dispose of all or substantially all of our assets related to GPU products and related technology to any third party
without The Foundry Company’s consent, unless the transferee agrees to be bound by the terms of the Wafer
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