Adaptec 2002 Annual Report Download - page 10

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RESEARCH AND DEVELOPMENT
Our current research and development efforts are targeted at integrating multiple channels or functions on
single chips, broadening the number of products we provide to address varying protocols and networking
functions, and increasing the speeds at which our chips operate.
At the end of fiscal 2002, we had design centers in the United States (California, Oregon, Maryland, and
Pennsylvania), Canada (British Columbia, Saskatchewan, Manitoba, Ontario and Quebec), Ireland, and India. On
January 16, 2003, we announced a corporate restructuring to further reduce our operating expenses. As a
result of this restructuring, we will be closing our design centers in Maryland, Ireland and India during
2003.
We spent $137.7 million in 2002, $201.1 million in 2001, and $178.8 million in
2000 on research and development.
In 2000, we also expensed $38.2 million of in process research and development, $31.5 million of which
related to the acquisition of Malleable Technologies and $6.7 million of which related to the acquisition of
Datum Telegraphic.
BACKLOG
We sell primarily pursuant to standard purchase orders. Our customers frequently revise the quantity
actually purchased and the shipment schedules to reflect changes in their needs. We believe orders placed
for delivery in excess of six months are not firm orders. As of December 31, 2002, our backlog of products
scheduled for shipment within six months totaled $36.6 million. Unless our customers cancel or defer to a
subsequent year a portion of this backlog, we expect this entire backlog to be filled in 2003. Our backlog
of products as of December 31, 2001 for shipment within six months totaled $35.7 million.
Our backlog includes backlog to our major distributor, which may not result in revenue, as we do not
recognize shipments to our major distributor as revenue until our distributor has sold our products through
to the end customer. Also, our customers may cancel, or defer to a future period, a significant portion of
the backlog at their discretion without penalty. Accordingly, we believe that our backlog at any given time
is not a meaningful indicator of future revenues.
COMPETITION
We typically face competition at the design stage when our networking customers determine which
communications semiconductor components to use in their next generation equipment designs.
Most of our customers choose a particular semiconductor component primarily
based on whether the component:
o meets the functional requirements,
o addresses the required protocols,
o interfaces easily with other components in a design,
o meets power usage requirements, and
o is priced competitively.
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